ADC characterization for high-speed applications

There is a rapid development of the performance of state-of-the-art analog to digital converters (ADC). Resolution and sampling rate are increasing continuously. Sampling rates in the high intermediate frequency (IF) range with sufficient dynamic range for communication applications were introduced about the turn of the millennium. Post-correction methods enable fast ADCs with modest linearity, and thereby weak dynamic performance, for high-speed applications. A post-correction procedure involves a characterization of the ADC non-linearity and then utilizing this information by processing the ADC output samples to remove the distortion. ADC characterization is usually performed by estimating ADC characteristics from measurements. Consequently, successful characterizations require both developed test methods and high performance test-beds. Characterization and testing ADCs are interesting in many different aspects. Not only that a proper characterization can be used for error compensation, testing is a major factor of cost for manufacturers, and shortening of the test cycle implies large savings. Testing ADCs is complicated, time consuming and demands high-performance instrumentation. TEST-BED AND DEVICE UNDER TEST The ADC test-bed is composed of commercial state-of-the-art instruments and components designed for this test-bed. Although it is designed to accomplish the general test set-ups described in IEEE standard 1241-2000 [1], it also can be used for general purpose. An overview of the test set-up is shown in Figure 1.